A Novel Power Optimization Technique for Ultra-Low Power RFICs

Author

Shameli, Amin ; Heydari, Payam

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Irvine, CA

fYear

2006

fDate

4-6 Oct. 2006

Firstpage

274

Lastpage

279

Abstract

This paper presents a novel power optimization technique for ultra-low power (ULP) RFICs. A new figure of merit, namely the g_mf_T- to-current ratio (g_mf_T/I_D), is defined for a MOS transistor, which accounts for both the unity-gain frequency and current consumption. It is demonstrated both analytically and experimentally that the g_mf_T/I_D reaches its maximum value in moderate inversion region. Next, using the proposed method, a power optimized common-gate low-noise amplifier (LNA) with active load has been designed and fabricated in a CMOS 0.18mum process operating at 950MHz. Measurement results show a noise-figure (NF) of 4.9dB and a small signal gain of 15.6dB with a record-breaking power dissipation of only 100muW

Keywords

CMOS integrated circuits; MOSFET; UHF amplifiers; circuit optimisation; low noise amplifiers; radiofrequency integrated circuits; 0.18 micron; 100 muW; 15.6 dB; 4.9 dB; 950 MHz; CMOS process; LNA; MOS transistor; ULP RFIC; common-gate low-noise amplifier; current consumption; merit figure; moderate inversion region; noise figure; power dissipation; power optimization technique; ultra low power RFIC; unity-gain frequency; CMOS process; Design optimization; Frequency; Gain measurement; Low-noise amplifiers; MOSFETs; Noise measurement; Power dissipation; Power measurement; Radiofrequency integrated circuits; CMOS; Design; Measurement; Ultra-low power; low-noise amplifier; radio-frequency integrated circuit;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Conference_Location

Tegernsee

Print_ISBN

1-59593-462-6

Type

conf

DOI

10.1109/LPE.2006.4271849

Filename

4271849