A three-million-transistor microprocessor

Author

Abu-Nofal, F. ; Avra, R. ; Bhabuthmal, K. ; Bhamidipaty, R. ; Blanck, G. ; Charnas, A. ; DelVecchio, P. ; Grass, J. ; Grinberg, J. ; Hayes, N. ; Haber, G. ; Hunt, J. ; Kizhepat, G. ; Malamy, A. ; Marston, A. ; Mehta, K. ; Nanda, S. ; Van Nguyen, H. ; Pate

Author_Institution

Sun MicroSystems, Mountain View, CA, USA

fYear

1992

fDate

19-21 Feb. 1992

Firstpage

108

Lastpage

109

Abstract

Describes a RISC (reduced-instruction-set computer) BiCMOS superscalar microprocessor containing 3.1 M transistors which executes up to three instructions per clock cycle. Clock frequency is 40 MHz with 8 mW dissipation. The chip includes a 32-b integer pipeline (IU), a memory management unit (MMU), a 20-kB instruction cache (I cache), a 16-kB data cache (D cache), an IEEE-compatible double-precision floating-point unit (FU), and a bus interface (BU). The chip supports built-in self-test, internal and JTAG boundary scan, in-circuit emulation for remote symbolic source-code debugging, and hardware to support multiprocessor system architecture. An on-chip phase-locked loop synchronizes external and internal clock edges. The chip is implemented in a 0.8- mu m triple-layer-metal salacided BiCMOS process. The die is 15.98*15.98 mm/sup 2/, with 166 active pins and 127 power/ground pins.<>

Keywords

BiCMOS integrated circuits; boundary scan testing; buffer storage; built-in self test; microprocessor chips; pipeline processing; reduced instruction set computing; 40 MHz; 8 mW; BiCMOS superscalar microprocessor; IEEE-compatible double-precision floating-point unit; JTAG boundary scan; RISC; built-in self-test; bus interface; clock cycle; clock edges; clock frequency; data cache; in-circuit emulation; instruction cache; integer pipeline; memory management unit; multiprocessor system; power dissipation; remote symbolic source-code debugging; triple-layer-metal salacided BiCMOS process; BiCMOS integrated circuits; Built-in self-test; Clocks; Computer aided instruction; Frequency; Memory management; Microprocessors; Pins; Pipelines; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0573-6

Type

conf

DOI

10.1109/ISSCC.1992.200435

Filename

200435