A study of signal integrity issues in through-silicon-via-based 3D ICs

Author

Liu, Chang ; Lim, Sung Kyu

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2010

fDate

6-9 June 2010

Firstpage

1

Lastpage

3

Abstract

In this paper, we study the signal integrity issues of through-silicon-via (TSV)-based 3D IC layouts. Unlike the most existing work, our study reports the coupling noise among all nets and all TSVs used in a real processor design implemented in 3D. Our RTL-to-GDSII design flow consists of commercial tools, enhanced with various add-ons to handle TSV and 3D stacking. Using this tool flow, we generate GDSII-level layouts of 3D implementation and perform sign-off-level signal integrity analysis. Based on our 2D vs 3D GDSII comparisons, we found that the overall noise-level of 3D is worse than 2D, but 3D designs have the advantage of significantly reducing the total number of the nosiest nets.

Keywords

integrated circuit layout; integrated circuit noise; three-dimensional integrated circuits; 3D stacking; RTL-to-GDSII design; TSV-based 3D IC layout; coupling noise; signal integrity; through-silicon-via; Capacitance; Integrated circuit interconnections; Integrated circuit noise; LAN interconnection; Process design; Routing; Stacking; Three-dimensional integrated circuits; Through-silicon vias; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2010 International

Conference_Location

Burlingame, CA

Print_ISBN

978-1-4244-7676-3

Type

conf

DOI

10.1109/IITC.2010.5510738

Filename

5510738