A BiCMOS 50 MHz cache controller for a superscalar microprocessor

Author

Joshi, B. ; Anand, R.K. ; Berg, C. ; Cruz-Rios, J. ; Krishnamurthi, A. ; Nettleton, N. ; Nguyen, S. ; Reaves, J. ; Reed, J. ; Rogers, A. ; Rusu, S. ; Tucker, C. ; Wang, C. ; Wong, M. ; Yee, D. ; Chang, J.-H.

Author_Institution

Sun Microsystems Computer Corp., Mountain View, CA, USA

fYear

1992

fDate

19-21 Feb. 1992

Firstpage

110

Lastpage

111

Abstract

A description is given of a BiCMOS 50-MHz, 2.2 M-transistor cache controller (CC) chip which supports up to 2 MB of direct-mapped secondary cache for a superscalar microprocessor chip (PU) and interfaces with two multiprocessor (MP) buses. One is the MBus, a circuit-switched MP system bus operating at TTL (transistor-transistor logic) levels. The other is the XBus, a local packet-switched bus operating at either TTL or Gunning-transceiver logic (GTL) levels. In XBus mode, the CC connects to MP buses through buswatcher chips, up to four of which can be connected to the CC to support 4 MP buses. With XBus interface, the CC can support customized MP buses.<>

Keywords

BiCMOS integrated circuits; buffer storage; microprocessor chips; storage management chips; system buses; 2 MB; 50 MHz; BiCMOS; Gunning-transceiver logic; MBus; TTL; XBus; buswatcher chips; cache controller; circuit-switched MP system bus; direct-mapped secondary cache; multiprocessor buses; packet-switched bus; superscalar microprocessor; BiCMOS integrated circuits; Charge pumps; Clocks; MOS devices; Microprocessors; Phase frequency detector; Phase locked loops; Synchronization; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0573-6

Type

conf

DOI

10.1109/ISSCC.1992.200436

Filename

200436