Title :
Prioritization of Paths for Diagnosis
Author :
Adapa, Rajsekhar ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng, Southern Illinois Univ., Carbondale, IL
Abstract :
Existing techniques for path delay fault (PDF) diagnosis do not provide high diagnostic resolution. These techniques fail to prune a large number of fault free candidates from the set of possible candidate faults. This paper presents an efficient technique to prioritize faults (PDFs) among the set of possible candidate faults. A novel approach for PDF prioritization is presented and its effectiveness is demonstrated on the ISCAS benchmarks.
Keywords :
VLSI; delays; fault diagnosis; network analysis; timing; fault free candidates; high diagnostic resolution; path delay fault diagnosis; possible candidate faults; prioritize faults; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Delay effects; Delay estimation; Failure analysis; Fault detection; Fault diagnosis; Timing; Failure Analysis; Fault Diagnosis; Path Delay Faults;
Conference_Titel :
Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
978-0-7695-3365-0
DOI :
10.1109/DFT.2008.46
