Design for Test Challenges of High Performance/Low Power Microprocessors

In this presentation, we are going to describe some of the architectural features of high performance/low power microprocessors. We then explain their unique test challenges due to their architecture and why these devices are different from ASICs designs from a test perspective. In addition, we present some of the commonly used DFT techniques, e.g., scan- based, memory BIST, IEEE 1149.1, and describe why these test techniques need to accommodate the architecture uniqueness of these microprocessors. Furthermore, we explain why the presented structural DFT techniques are necessary, yet not sufficient for a complete test of these devices. We continue the presentation with describing the architecture support requirement for using functional test vectors.