Defect-Tolerant Hybrid CMOS/Nanoelectronic Circuits

Summary form only given. This paper reviews recent work on devices, circuits and defect-tolerant architectures for hybrid semiconductor/nanodevice integrated circuits. Such a circuit is essentially a CMOS stack with a simple add-on in the form of a nanowire crossbar, with similar two-terminal devices (with the functionality of programmable diodes) formed at each crosspoint. Special attention was given to the so-called "CMOL" variety of the hybrids, in which the crossbar is connected to the CMOS circuit with an area-distributed interface. Such interface allows the CMOS subsystem to address each and every of the crosspoint devices, even with no nanoscale alignment between the CMOS and crossbar subsystems. The recent detailed studies have shown CMOL may enable (at least) the following applications: (i) terabit-scale memories with access time below 100 ns and defect tolerance up to 10%, (ii) FPGA-like reconfigurable logic circuits with even higher (~20%) defect tolerance, and the density at least two orders of magnitude lower than that of CMOS FPGAs fabricated with similar design rules and power per unit area, and (iii) mixed-signal neuromorphic networks ("CrossNets") which may exhibit extraordinary defect tolerance (up to 90%) and provide unparalleled performance for some important information processing tasks. Recently, the hybrid circuit concept has received a strong boost from the experimental demonstrations of reproducible crosspoint devices (programmable diodes) based on amorphous silicon, and nanowire crossbars with 15-nm-scale half-pitch. However, the transfer of semiconductor IC industry to the hybrid technology still requires a very substantial effort, and the paper describes the most significant challenges on that way. References may be found at http://rsfql.physics.sunysb.edu/~likharev/nano/.