DocumentCode :
3038993
Title :
Hardware implementation of Grain-128, Mickey-128, Decim-128 and Trivium
Author :
Marmolejo-Tejada, J.M. ; Trujillo-Olaya, V. ; Velasco-Medina, J.
Author_Institution :
Bionanoelectronics Res. Group, Univ. del Valle, Cali, Colombia
fYear :
2010
fDate :
15-17 Sept. 2010
Firstpage :
1
Lastpage :
6
Abstract :
This work presents the hardware implementation of four hardware profile stream ciphers from the eSTREAM project. The hardware architectures are implemented using structural VHDL and, taking into account the simulation results, the best algorithm for hardware implementation is Trivium, with an 80-bit security level. This implementation requires 8 ALUTs, 289 registers, has a maximum frequency of 915.75 MHz and a throughput of 915 Mbps. The second is Grain-128, followed by Mickey-128 and Decim-128, which have a 128-bit security level. The designs were synthesized on the Altera FPGA Stratix III EP3SE50F484C2.
Keywords :
computer architecture; cryptography; hardware description languages; 289 registers; 8 ALUT; 80-bit security level; Decim-128; Grain-128; Mickey-128; Trivium; VHDL; eSTREAM project; hardware architectures; hardware implementation; hardware profile stream ciphers; Algorithm design and analysis; Field programmable gate arrays; Hardware; Security; Shift registers; Throughput; Decim-128; Grain-128; Mickey-128; Stream Cipher; Trivium; eSTREAM;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ANDESCON, 2010 IEEE
Conference_Location :
Bogota
Print_ISBN :
978-1-4244-6740-2
Type :
conf
DOI :
10.1109/ANDESCON.2010.5632901
Filename :
5632901
Link To Document :
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