Path-finding for integration of porous SiOCH films (k∼2.5) in system-LSIs

Author

Inoue, N. ; Ueki, M. ; Yamamoto, H. ; Kume, I. ; Iguchi, M. ; Kaneko, T. ; Honda, H. ; Oshida, D. ; Ozawa, K. ; Ishizuka, I. ; Horikoshi, Y. ; Kawahara, J. ; Hayashi, Y.

Author_Institution

LSI Fundamental Res. Lab., NEC Electron. Corp., Sagamihara, Japan

fYear

2010

fDate

6-9 June 2010

Firstpage

1

Lastpage

3

Abstract

Impacts of k-value reduction on LSI performances are clarified quantitatively using 2M-gate net-list. Reduction in k-value from 3.0 to 2.5 for M2-M5 interconnect layers achieves 11%-drop in interconnect parasitic capacitance (C_int) and 8.4%-reduction in propagation delay (τ_d), which also shrinks the effective variability of τ_d to improve LSI operation margins. From a viewpoint of BEOL fabrication with k~2.5, a carbon-rich porous SiOCH film has high tolerance to process-induced damages, resulting in lower C_int than that of an O-rich film with similar k-value. Sustainability to FCBGA packaging with Pb-free solder bumps is also confirmed for the multi-level interconnects with the C-rich porous SiOCH.

Keywords

ball grid arrays; integrated circuit interconnections; large scale integration; porous semiconductors; silicon compounds; 2M-gate net-list; BEOL fabrication; FCBGA packaging; Pb-free solder bump; SiOCH; interconnect parasitic capacitance; k-value reduction; path-finding; porous SiOCH Film; system-LSI; Circuit simulation; Delay estimation; Electronics packaging; Fabrication; Integrated circuit interconnections; Large scale integration; National electric code; Parasitic capacitance; Propagation delay; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2010 International

Conference_Location

Burlingame, CA

Print_ISBN

978-1-4244-7676-3

Type

conf

DOI

10.1109/IITC.2010.5510746

Filename

5510746