ESD detection circuit with reverse-used RC network in a 90-nm CMOS process

The gate leakage current issue in nanometer CMOS process is serious. An ESD detection circuit with reverse-used RC network is proposed in a 90-nm CMOS process. It reduces the leakage current in RC network by reducing the area of MOS capacitor and avoiding high voltage drop across MOS capacitor. The leakage current is 5.7 nA at 25°C. The total capacitor area used is only 4 μm². Under ESD event, it can generate 39 mA trigger current to turn on the SCR.