Low-power Fanout Optimization Using MTCMOS and Multi-Vt Techniques

Author

Amelifard, Behnam ; Fallah, Farzan ; Pedarm, Massoud

Author_Institution

Dept. of Electr. Eng.-Syst., Southern California Univ., Los Angeles, CA

fYear

2006

fDate

4-6 Oct. 2006

Firstpage

334

Lastpage

337

Abstract

This paper addresses the problem of low-power fanout optimization. We show that due to neglecting short-circuit current, previous analytical techniques proposed to optimize the area of a fanout tree may result in excessive power consumption. This show to achieve a low-power fanout tree, an accurate power consumption model should be used as the objective function. Moreover, we propose an efficient method to minimize the total power consumption of a fanout tree by using MTCMOS and multi-Vt techniques. Experimental results show that depending on the activity factor of the circuit, the proposed technique can reduce the power consumption of the fanout tree 18% to 45%

Keywords

CMOS logic circuits; circuit simulation; integrated circuit design; logic design; logic gates; low-power electronics; minimisation; MTCMOS; buffer chain; fanout optimization; fanout tree; low-power design; multiVt techniques; objective function; power consumption minimization; short-circuit current; Algorithm design and analysis; Circuit synthesis; Delay; Design optimization; Energy consumption; Inverters; Laboratories; Parasitic capacitance; Power dissipation; Topology; Algorithms; Design; Low-power design; Performance; buffer chain; fanout optimization; fanout tree;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Conference_Location

Tegernsee

Print_ISBN

1-59593-462-6

Type

conf

DOI

10.1109/LPE.2006.4271860

Filename

4271860