Attributes of parallel and cascade microprocessor implementations of digital signal processing

Microprocessors have achieved great popularity because they are inexpensive, convenient, and flexible. A microprocessor with an architecture chosen to efficiently perform digital signal processing algorithms would retain these advantages when used to implement digital signal processing. One such architecture is the Research Signal Processor (RSP) which was designed by Abraham Peled and constructed at the IBM Thomas J. Watson Research Center. In order for the RSP to be cost effective, however, it must be capable of implementing a wide range of problems so that the cost of developing an LSI version can be borne by many applications. The potential applications, however, vary greatly in size. A microprocessor capable of implementing the largest of these applications would be expensive and underutilized for many others. The approach we have chosen is to implement modestly sized applications with a single RSP, and to distribute larger applications over several RSPs. In the hope of keeping the cost of this distribution small, two simple structures, the parallel and cascade clusters were first investigated. This paper presents the attributes of these structures when used to implement the FFT, FIR filters and IIR filters. The types of data transfers required to implement these algorithms are also found, and the I/O capabilities of the RSP chosen to perform these transfers are presented.