An 8 G connections-per-second 54 mW digital neural network chip low-power chain-reaction architecture

Author

Uchimura, K. ; Saito, Osamu ; Amemiya, Y.

Author_Institution

NTT LSI Lab., Atsugi, Japan

fYear

1992

fDate

19-21 Feb. 1992

Firstpage

134

Lastpage

135

Abstract

A high-speed digital neural-network chip which uses a polyhedric discrimination neuron (PDN) model and a low-power chain-reaction (LCR) architecture is presented. The chip contains 832 fully implemented digital synapse units with 8-b weights which form 13 neurons on a 10.3*14.1 mm/sup 2/ die using 0.8- mu m CMOS technology. A computational speed of 8 billion connections-per-second (GCPS) is achieved with 54-mW power dissipation. The forward propagation time of 104 ns is the fastest reported for a digital neural network chip. These features make possible large-scale neural network chips and systems.<>

Keywords

CMOS integrated circuits; large scale integration; neural nets; 0.8 micron; 104 ns; 54 mW; CMOS technology; chain-reaction architecture; computational speed; digital neural network chip; digital synapse units; forward propagation time; large-scale neural network chips; polyhedric discrimination neuron; Adders; Automatic control; CMOS technology; Clocks; Computer architecture; Integrated circuit interconnections; Neural networks; Neurons; Power dissipation; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0573-6

Type

conf

DOI

10.1109/ISSCC.1992.200448

Filename

200448