Title :
Sub-Threshold Design: The Challenges of Minimizing Circuit Energy
Author :
Calhoun, B.H. ; Wang, A. ; Verma, N. ; Chandrakasan, A.
Author_Institution :
Virginia Univ., Charlottesville, VA
Abstract :
In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges
Keywords :
CMOS digital integrated circuits; integrated circuit design; low-power electronics; microprocessor chips; dynamic voltage scaling; fabricated chips; low voltage memory; minimizing circuit energy; process variations; sub-threshold circuit design; sub-threshold digital circuits; sub-threshold logic; CMOS logic circuits; CMOS process; Circuit synthesis; Delay; Digital circuits; Dynamic voltage scaling; Logic circuits; Logic design; Ring oscillators; Robustness; Design; Performance; Reliability; Sub-threshold digital circuits; dynamic voltage scaling; low voltage memoty; process variations; sub-threshold logic;
Conference_Titel :
Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on
Conference_Location :
Tegernsee
Print_ISBN :
1-59593-462-6
DOI :
10.1109/LPE.2006.4271869
