A 2 M-pixel two-level vertically integrated HDTV image sensor

Author

Shibata, H. ; Inoue, I. ; Miyagawa, R. ; Yamashita, H. ; Nohmi, N. ; Furukawa, A. ; Iida, Yuki ; Yamaguchi, T. ; Endo, Y. ; Matsunaga, Y. ; Manabe, S.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1992

fDate

19-21 Feb. 1992

Firstpage

166

Lastpage

167

Abstract

A 2 Mpixel two-level CCD (charge-coupled device) image sensor which has no capacitive image lag is discussed. Image lag is reduced to 0.4% and the dynamic range expanded from 72 dB to 110 dB. A schematic diagram of this device is shown. The pixel structure adopts an additional storage-diode-resetting gate (SRG) and bias-charge-injecting diode (CID) formed adjacent to a vertical CCD. A single CID is shared by two horizontally adjacent pixels, allowing the charge to be injected into two storage diodes simultaneously.<>

Keywords

CCD image sensors; high definition television; 2 Mpixel; HDTV image sensor; bias-charge-injecting diode; dynamic range; image lag; pixel structure; storage-diode-resetting gate; vertically integrated image sensor; Amorphous silicon; Blanking; Charge-coupled image sensors; Diodes; Dynamic range; HDTV; Image sensors; Photoconducting devices; Ultra large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0573-6

Type

conf

DOI

10.1109/ISSCC.1992.200463

Filename

200463