LDGR: An efficient load-balancing inter Dimension Group Routing selection strategy in on-chip networks

Load balance is critical to the performance of adaptive routing algorithm for on-chip interconnection networks. Load Balance is mainly depended on the algorithm´s selection strategy which is employed when the algorithm´s routing function returns more than one admissible output ports. Existing selection strategies use local congestion metrics to make a port selection decision while ignore the global congestion condition, thus results in sub-optimal selections. In this paper, we propose an efficient Load-balancing inter Dimension Group Routing selection strategy (LDGR) in on-chip networks. The proposed selection strategy takes into account the neighbor´s free VC count when make a routing decision. LDGR can achieve load balance over a wider area beyond local area by balancing the load of both X dimension link group and Y dimension link group. The evaluation result indicates that the proposed method outperforms local selection strategy in throughput about 13.4% on average under synthetic traffics patterns on 8×8 mesh topology.