A 1 V TFT-load SRAM using a two-step word-voltage method

Author

Ishibashi, K. ; Takasugi, K.-I. ; Yamanaka, T. ; Hashimoto, T. ; Sasaki, K.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1992

fDate

19-21 Feb. 1992

Firstpage

206

Lastpage

207

Abstract

A 1-V battery-operated SRAM with a 10.2- mu m/sup 2/ TFT (thin-film transistor) load cell is described which uses a two-step word-voltage (TSW) method, a level-shift sense amplifier, and a 0.23- mu A boosted-level generator. By using these means, a 0.7- mu A-standby-current 4-Mb SRAM with 75-mm/sup 2/ chip can be installed in a terminal using a single 1.2-V battery. The measured currents and output voltages of the boosted-level generator in the standby model are shown, and the characteristics of a 4-kB test chip fabricated using a 0.4- mu m CMOS technology are listed along with the process parameters. Operating waveforms of the 4-kb SRAM are shown.<>

Keywords

CMOS integrated circuits; SRAM chips; VLSI; 0.23 muA; 0.4 micron; 0.7 muA; 1 V SRAM; 1 to 1.2 V; 4 Mbit; 4 kbit; CMOS SRAM; CMOS technology; TFT-load; ULSI; battery-operated SRAM; boosted-level generator; level-shift sense amplifier; process parameters; test chip; thin-film transistor; two-step word-voltage method; waveforms; Battery charge measurement; CMOS technology; Character generation; Current measurement; Random access memory; Semiconductor device measurement; Semiconductor device modeling; Standby generators; Thin film transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0573-6

Type

conf

DOI

10.1109/ISSCC.1992.200484

Filename

200484