NBTI life time of a high voltage PMOS FET

We present a study on NBTI life time for high voltage PMOS transistors. These devices are used in erasing and programming control circuits for a floating-gate flash based FPGA array fabricated with a 65nm embedded process. NBTI stress tests were performed with different gate biases and at different temperatures. Life time model parameters, such as voltage acceleration factor and activation energy, were obtained from the tested results. NBTI device life time was assessed against product requirements. A 50 times (50X) margin in life time was estimated for our baseline process, based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or completely depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases. To further improve NBTI lifetime margin against product requirement, LDD doping was increased and optimized. We are able to further improve HV PMOS device performance in this regard.