A 7 ns 140 mW 1 Mb CMOS SRAM with current sense amplifier

Author

Sasaki, K. ; Ishibashi, K. ; Ueda, K. ; Komiyaji, K. ; Yamanaka, T. ; Hashimoto, N. ; Toyoshima, H. ; Kojima, F. ; Shimizu, A.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1992

fDate

19-21 Feb. 1992

Firstpage

208

Lastpage

209

Abstract

A 1-Mb CMOS SRAM uses a high-speed current-sense amplifier and a pre-output buffer designed for 3-V power supply to achieve 7-ns access and 140-mW power dissipation. A 6.6- mu m/sup 2/ cell is achieved using 0.3- mu m CMOS technology with phase-shifting photolithography. Soft-error immunity can be drastically improved by the cross-coupled resistances built into the polysilicon pMOS transistors without increasing the cell area or process complexity.<>

Keywords

CMOS integrated circuits; SRAM chips; VLSI; 0.3 micron; 1 Mbit; 140 mW; 3 V; 3 V SRAM; 7 ns; CMOS SRAM; ULSI; access time; cell area; cross-coupled resistances; current sense amplifier; low voltage SRAM; phase-shifting photolithography; polysilicon pMOS transistors; power dissipation; power supply; pre-output buffer; process complexity; supply voltage; CMOS technology; Circuits; Current supplies; Delay; Laboratories; MOSFETs; Power dissipation; Pulse amplifiers; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0573-6

Type

conf

DOI

10.1109/ISSCC.1992.200485

Filename

200485