Title :
A 9 ns 4 Mb BiCMOS SRAM with 3.3 V operation
Author :
Kato, H. ; Suzuki, A. ; Hamano, T. ; Kobayashi, T. ; Sato, K. ; Nakayama, T. ; Gojohbori, H. ; Maeda, T. ; Ochii, K.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A description is given of a 4-Mb TTL (transistor-transistor logic) SRAM in 0.5- mu m BiCMOS technology which uses scaled-down features of optimized MOS and bipolar transistors and BinMOS circuits to achieve 9 ns access and low-power 3.3-V operation of a 16-b organization. The SRAM block diagram is presented, and the 0.5- mu m triple-polysilicon and double-metal BiCMOS process is summarized.<>
Keywords :
BiCMOS integrated circuits; SRAM chips; VLSI; transistor-transistor logic; 16 bit; 18.8 mm; 3.3 V operation; BiCMOS SRAM; TTL BiCMOS SRAM; ULSI; block diagram; double-metal; organization; scaled-down features; triple-polysilicon; BiCMOS integrated circuits; CMOS technology; Capacitance; Decoding; Electrodes; Propagation delay; Random access memory; Semiconductor devices; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200486
