Title :
A 15 ns 16 Mb CMOS SRAM with reduced voltage amplitude data bus
Author :
Matsumiya, M. ; Kawashima, S. ; Sakata, M. ; Miyabo, T. ; Koga, T. ; Itabashi, K. ; Mizutani, K. ; Ema, T. ; Toyoda, K. ; Yabu, T. ; Shimada, H. ; Suzuki, N. ; Ookura, M.
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
Abstract :
A 15-ns 16-Mbit CMOS SRAM which uses a reduced voltage amplitude data bus and a hierarchical sense amplifier scheme is described. The SRAM is organized as 4 Mwords*4 bits. Fast access time and low power dissipation are obtained by a reduced-voltage-amplitude data bus connected to a latched cascaded sense amplifier and current sense amplifier. The waveforms of the address input and the data output lines at room temperature with a 3-V supply are shown. The access time is typically 15 ns, with an active current consumption of 55 mA at 3.0 V and 30 MHz.<>
Keywords :
CMOS integrated circuits; SRAM chips; VLSI; 15 ns; 16 Mbit; 165 mW; 3 V; 3 V SRAM; 30 MHz; 4 bit; 55 mA; CMOS SRAM; ULSI; access time; current consumption; current sense amplifier; hierarchical sense amplifier scheme; latched cascaded sense amplifier; power dissipation; reduced voltage amplitude data bus; Circuits; Current measurement; Delay effects; Energy consumption; Lithography; Power dissipation; Random access memory; Semiconductor device measurement; Thin film transistors; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200488
