DocumentCode :
3039769
Title :
Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process
Author :
Milner, David ; Baldwin, Daniel F.
Author_Institution :
George W. Woodruff Sch. of Mech. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
2001
fDate :
2001
Firstpage :
51
Lastpage :
56
Abstract :
Voiding is a concern in low cost, high throughput, or “no-flow” flip chip assembly. This process involves chip placement directly on the pad site with pre-dispensed no-flow underfill on it. The forced motion causes a convex flow front to pass over pad and mask-opening features, promoting void capture. This paper determines the effects of substrate design on underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing, including pad height, solder mask opening height, pad/solder mask opening separation, pad pitch, chip placement speed, and underfill viscosity. Test substrates were designed and manufactured at Georgia Tech´s Packaging Research Center to ensure process control. The design consisted of 6 factors with a mix of levels for each. These included four levels of copper pad heights, two solder mask opening heights, three pad/solder mask separation distances between copper pad and solder mask opening edges, three feature (pad/mask openings) pitches, two chip placement speeds and four pad/mask geometries separated into pad site quadrants. The experiments involve placement of a transparent glass chip on the pad site through a predispensed no-flow underfill. Subsequent flow of the underfill is carefully recorded and resultant voids are logged and analyzed. The response variable is defined as the number of voids created in the process, and is further analyzed for the location and any visible modes of void formation. Thus, improved substrate designs can be derived
Keywords :
design of experiments; encapsulation; flip-chip devices; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; masks; microassembling; soldering; voids (solid); Cu; chip placement; chip placement speed; convex flow front; copper pad; copper pad height; design factors; feature pitch; flip chip assembly process; full-factorial design experiment; mask opening pitch; mask-opening features; no-flow flip chip assembly; no-flow process; no-flow processing; pad features; pad height; pad pitch; pad site; pad site quadrants; pad/mask geometries; pad/solder mask opening separation; pad/solder mask separation distance; pre-dispensed no-flow underfill; predispensed no-flow underfill; process control; response variable; solder mask opening edge; solder mask opening height; substrate design; test substrate design; throughput; transparent glass chip placement; underfill flow; underfill viscosity; underfill voiding; void capture; void formation modes; void location; voids; Assembly; Copper; Costs; Flip chip; Manufacturing processes; Packaging; Process design; Testing; Throughput; Viscosity;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Packaging Materials: Processes, Properties and Interfaces, 2001. Proceedings. International Symposium on
Conference_Location :
Braselton, GA
Print_ISBN :
0-930815-64-5
Type :
conf
DOI :
10.1109/ISAOM.2001.916548
Filename :
916548
Link To Document :
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