Effect of via geometry on thermal stress in dual-damascene Cu interconnects

The thermal stress in dual-damascene Cu interconnects with different via geometry and dielectric materials combination was simulated using the finite element method. The simulation results are presented to show that a small via linked to a wide and large Cu block increases the risk of electro-migration and stress migration failure. Vias in cylinders will drastically reduce thermal stress of the entire structure which is prone to undertake shear strain and increase, to some extent, the thermal stress level on the top plane of lower Cu block simultaneously. The thermal stress distribution is sensitive to the structure, especially when low-A materials are involved. Partial combination of dielectric materials such as SiO₂ and SiLK is not expected to change the thermal stress distributions obviously.