Title :
A 5 Gb/s 16*16 Si-bipolar crosspoint switch
Author :
Shin, H. ; Warnock, J. ; Immediato, M. ; Chin, K. ; Chuang, C.-T. ; Cribb, M. ; Heidel, D. ; Sun, Y.-C. ; Mazzeo, N. ; Brodsky, S.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
An experimental 16*16, nonblocking, asynchronous crosspoint switch with 5 Gb/s channel data rate is described. Implemented in a 0.8- mu m, double-poly, self-aligned Si-bipolar ECL (emitter coupled logic) technology, the 3*3 mm/sup 2/ chip with a multiplexer-type architecture and a three-device crosspoint cell features a data path delay of 420 ps and a set-up time of 1 ns, and dissipates about 4.6 W. Signal levels are ECL compatible. This crosspoint which supports selective or full broadcasting and a simple expansion mechanism.<>
Keywords :
bipolar integrated circuits; electronic switching systems; emitter-coupled logic; semiconductor switches; silicon; 0.8 micron; 1 ns; 3 mm; 4.6 W; 420 ps; 5 Gbit/s; ECL compatibility; ECL signal level; Si chip; asynchronous crosspoint switch; channel data rate; data path delay; expansion mechanism; full broadcasting; multiplexer-type architecture; nonblocking; self-aligned Si-bipolar ECL; set-up time; three-device crosspoint cell; Clocks; Decoding; Latches; Multiplexing; Power supplies; Propagation delay; Semiconductor device measurement; Switches; Switching circuits; Timing jitter;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200495
