Hardware timebase calibration in the multi-GSa/s LABRADOR-4 ASIC

In recent years inexpensive, multi-Giga sample per second CMOS waveform samplers have become available, enabling a new generation of low-power, high channel count experiments in particle and astroparticle physics. Power savings over other architectures is realized by having nothing operating at the direct sampling rate of interest. Instead, the Switched Capacitor Array sampling is driven by timing generators based upon voltage-controlled delay lines. Stabilization of the timebase and the significant calibration effort required, due to the non-uniform time-steps introduced by CMOS process variations in these delay lines, have limited their more wide-spread adoption in the community. In most of the CMOS processes used, the sample-to-sample time step difference is of order 10-20%, and cannot be neglected in many applications. Especially for applications involving real-time processing of the waveform samples from these devices, splining and resampling the smoothed waveforms on a uniform time grid is computationally very expensive. To address this issue, in the 4th generation LABRADOR ASIC, individual time sample trim DACs have been implemented to tune out this time step variance. Available results of this hardware-level calibration are reported.