An integrated circuit for speech synthesis

Stringent requirements concerning vocabulary size, cost and speech quality were imposed on the voice response system for a low cost consumer product. In order to satisfy these requirements a one chip speech synthesizer based on the technique of linear prediction was designed. This PMOS synthesizer circuit contains a pipelined multiplier, an adder, and several shift registers contained in a special purpose processing architecture. Combined with the proper computational ordering, this allows an efficient implementation of the all-pole lattice filter. The synthesizer input is a bit stream specifying the parameters of energy, pitch and 10 reflection coefficients.