0.29-/spl mu/m/sup 2/ trench cell technologies for 1G-bit DRAMs with open/folded-bit-line layout and selective growth technique

Author

Noguchi, M. ; Ozaki, T. ; Aoki, M. ; Hamamoto, T. ; Habu, M. ; Kato, Y. ; Takigami, Y. ; Shibata, T. ; Nakasugi, T. ; Niiyama, H. ; Tokano, K. ; Saito, Y. ; Hoshi, T. ; Watanabe, S.

Author_Institution

Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan

fYear

1995

fDate

6-8 June 1995

Firstpage

137

Lastpage

138

Abstract

We present substrate-plate-trench cell technologies for 1G-bit DRAMs. With an open/folded-bit-line layout, the smallest cell area of 0.29 /spl mu/m/sup 2/ was realized for a 0.20 /spl mu/m design rule. A pause time of 4.2 s at 85/spl deg/C and an activation energy of 0.70 eV were achieved for a 0.25-/spl mu/m/spl Phi//spl times/4-/spl mu/m trench capacitor. A new Si selective epitaxial growth (SEG) technique was developed to reduce connection formation between the capacitor and transistor to one fabrication step, and also reduce a distance between the trench and gate. The gate capacitors on the SEG showed a breakdown electric field over 11 MV/cm even when the distance was less than 0.1 /spl mu/m.

Keywords

CMOS memory circuits; DRAM chips; VLSI; integrated circuit layout; integrated circuit technology; vapour phase epitaxial growth; 0.2 micron; 1 Gbit; 4.2 s; 85 C; DRAMs; SEG technique; Si; Si selective epitaxial growth; breakdown electric field; fabrication; gate capacitors; open/folded-bit-line layout; substrate-plate-trench cell technologies; Capacitors; Costs; Dielectrics; Electric breakdown; Epitaxial growth; Fabrication; Random access memory; Research and development; Semiconductor device noise; Semiconductor materials;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

0-7803-2602-4

Type

conf

DOI

10.1109/VLSIT.1995.520895

Filename

520895