Title :
VIDE: a visual VHDL integrated design environment
Author :
Bian, Jinian ; Xue, Hongxi ; Su, Ming
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
In this paper, a high-level design system called VIDE (Visual VHDL Integrated Design Environment) is presented. In VIDE, there are several graphical and textual mixed design entry tools (VDES=Visual Design Entry System) and a graphical object-oriented debugger (VDBG=Visual DeBuGger). VDES consists of several diagram editors and a visual text editor, while VDBG is a debugging environment based on a hierarchical VHDL simulator. The graphical objects can be specified as a debugging target
Keywords :
computer debugging; diagrams; engineering graphics; hardware description languages; high level synthesis; object-oriented programming; text editing; virtual machines; VDBG; VDES; VIDE; Visual Debugger; Visual Design Entry System; Visual VHDL Integrated Design Environment; debugging environment; debugging target; diagram editors; graphical design entry tools; graphical object specification; graphical object-oriented debugger; hierarchical VHDL simulator; high-level design system; textual design entry tools; visual text editor; Automata; Computer science; Debugging; Design for disassembly; Environmental management; Flow graphs; Graphical models; Hardware design languages; Libraries; Object oriented modeling;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
DOI :
10.1109/ASPDAC.1997.600258
