A new approach to the robust wirebonding

Author

Van Pham, Cuong ; Huth, Ken

fYear

2001

fDate

2001

Firstpage

379

Lastpage

385

Abstract

Electronics manufacturers are pursuing miniaturization in order to cope with the prevailing electronic trends. In doing so, they are faced with shrinking the size of silicon chips, while adding more functions (the number of the inputs and outputs, I/Os). However, the IC component yield decreases with the increase in I/Os, since the wirebonding process yield providing the interconnection for the I/Os remains constant. The bottom line is lower profits. Based on the diffusion theories behind wirebonding and the effects of both thermal and kinetic energies on the behavior of materials, the authors propose a model for a “robust” bond and an approach to obtain that model in the wirebonding process

Keywords

diffusion; integrated circuit interconnections; integrated circuit packaging; integrated circuit yield; lead bonding; semiconductor process modelling; IC component yield; Si; diffusion theories; electronics manufacture; interconnection; kinetic energy; materials behaviour; miniaturization; robust bond model; robust wirebonding; silicon chip I/Os; silicon chip functions; silicon chip inputs/outputs; silicon chip size reduction; thermal energy; wirebonding; wirebonding process; wirebonding process yield; Diffusion bonding; Geometry; Integrated circuit testing; Manufacturing; Materials testing; Robustness; Scanning probe microscopy; Silicon; Tail; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Packaging Materials: Processes, Properties and Interfaces, 2001. Proceedings. International Symposium on

Conference_Location

Braselton, GA

Print_ISBN

0-930815-64-5

Type

conf

DOI

10.1109/ISAOM.2001.916605

Filename

916605