A high performance 16M DRAM on a thin film SOI

Author

Hyoung-Sub Kim ; Sang-Bo Lee ; Dong-Uk Choi ; Jae-Hoon Shim ; Kyu-Han Lee ; Kyu-Pil Lee ; Ki-Nam Kim ; Jong-Woo Park

Author_Institution

Technol. Dev., Samsung Electron. Co., Kyungki, South Korea

fYear

1995

fDate

6-8 June 1995

Firstpage

143

Lastpage

144

Abstract

A fully working 16M DRAM on a Thin Film Silicon On Insulator (TFSOI) is made with 0.5 /spl mu/m CMOS technology. This is, to the best of our knowledge, the highest density SOI DRAM ever achieved. LOCOS isolation and Local Implantation post Field oxidation (LIF) are introduced to suppress the edge transistor effect in NMOS. A reduced n/sup +//p/sup +/ dose in S/D implantation is the key process for a high density TFSOI-DRAM to suppress the defect generation during process while drain-source breakdown voltage (BVds) being increased. The shmoo plot of supply voltage vs. TRAC at 25/spl deg/C for a TFSOI-DRAM is demonstrated. RAS access time, TRAC, is 50 ns at 3.0 V Vcc which is faster by 20% than that of the equivalent bulk-Si device.

Keywords

CMOS memory circuits; DRAM chips; ion implantation; isolation technology; silicon-on-insulator; 0.5 micron; 16 Mbit; 3 V; 50 ns; CMOS technology; LOCOS isolation; Si; drain-source breakdown voltage; dynamic RAM; edge transistor effect suppression; high performance DRAM; highest density SOI DRAM; local implantation post field oxidation; thin film SOI; Boron; Breakdown voltage; CMOS technology; Capacitors; Contact resistance; MOS devices; Oxidation; Random access memory; Silicon on insulator technology; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

0-7803-2602-4

Type

conf

DOI

10.1109/VLSIT.1995.520898

Filename

520898