Title :
Associative Memory for L1 track triggering in LHC environment
Author :
Annovi, A. ; Broccolo, G. ; Ciocci, A. ; Giannetti, P. ; Ligabue, F. ; Magalotti, D. ; Nappi, A. ; Dell´Orso, M. ; Dell´Orso, R. ; Palla, F. ; Pedreschi, E. ; Piendibene, M. ; Servoli, L. ; Taroni, Silvia ; Volpi, G.
Author_Institution :
INFN LNF, Frascati, Italy
Abstract :
The CDF Associative-Memory device (AM), proven technology developed for the Silicon-Vertex-Trigger at the CDF experiment, is one of the proposed solutions at the LHC for track reconstruction at level-1 in the HL-LHC upgrade, for very high-luminosity conditions (hundreds proton-proton collisions every 25 ns, at 5×1034 cm-2sec-1). This luminosity requires a drastic revision of the existing trigger strategies. In the CMS experiment, one of the identified challenges for future upgrades is the capability of using already at L1 the tracker information to trigger events. Simulation studies show that this can be achieved by correlating hits on two closely spaced silicon strip sensors. This strategy requires massive computing power, to minimize the online execution time of complex tracking algorithms and the “combinatorial challenge”. The AM allows to compare the tracker information of each event to pre-calculated “expectations” (pattern matching) in a so short time that tracks can contribute to the trigger decision. One of the main challenges for the CMS tracker is the latency due to the tracker data distribution to the AM processors. A very parallelized readout architecture and a possible layout are discussed.
Keywords :
nuclear electronics; particle tracks; pattern matching; position sensitive particle detectors; readout electronics; silicon radiation detectors; AM processors; CDF associative-memory device; CDF experiment; CMS experiment; CMS tracker; HL-LHC upgrade; L1 track triggering; LHC environment; closely spaced silicon strip sensors; complex tracking algorithms; high-luminosity conditions; level-1 track reconstruction; online execution time; parallelized readout architecture; pattern matching; proton+proton collisions; silicon-vertex-trigger; time 25 ns; tracker data distribution; Associative memory; Clocks; Detectors; Field programmable gate arrays; Program processors; Roads;
Conference_Titel :
Real Time Conference (RT), 2012 18th IEEE-NPSS
Conference_Location :
Berkeley, CA
Print_ISBN :
978-1-4673-1082-6
DOI :
10.1109/RTC.2012.6418193