DocumentCode :
3041329
Title :
A multiple LID routing scheme for fat-tree-based InfiniBand networks
Author :
Lin, Xuan-Yi ; Chung, Yeh-Ching ; Huang, Tai-Yi
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear :
2004
fDate :
26-30 April 2004
Firstpage :
11
Abstract :
Summary form only given. In a cluster system, performance of the interconnection network greatly affects the computation power generated together from all interconnected processing nodes. The network architecture, the interconnection topology, and the routing scheme are three key elements dominating the performance of an interconnection network. InfiniBand architecture (IBA) is a new industry standard architecture. It defines a high-bandwidth, high-speed, and low-latency message switching network that is good for constructing high-speed interconnection networks for cluster systems. Fat-trees are well-adopted as the topologies of interconnection networks because of many nice properties they have. We proposed an m-port n-tree approach to construct fat-tree-based InfiniBand networks. Based on the constructed fat-tree-based InfiniBand networks, we proposed an efficient multiple LID (MLID) routing scheme. The proposed routing scheme is composed of processing node addressing scheme, path selection scheme, and forwarding table assignment scheme. To evaluate the performance of the proposed routing scheme, we have developed a software simulator for InfiniBand networks. The simulation results show that the proposed routing scheme runs well on the constructed fat-tree-based InfiniBand networks and is able to efficiently utilize the bandwidth and the multiple paths that fat-tree topology offers under InfiniBand architecture.
Keywords :
multiprocessing systems; multiprocessor interconnection networks; open systems; performance evaluation; telecommunication network routing; trees (mathematics); workstation clusters; InfiniBand architecture; cluster system; fat-tree-based InfiniBand network; forwarding table assignment scheme; interconnection network; message switching network; multiple LID routing scheme; path selection scheme; processing node addressing scheme; software simulator; Bandwidth; Computer architecture; Computer networks; Computer science; Multiprocessor interconnection networks; Network topology; Packet switching; Power system interconnection; Routing; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International
Print_ISBN :
0-7695-2132-0
Type :
conf
DOI :
10.1109/IPDPS.2004.1302913
Filename :
1302913
Link To Document :
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