Application of statistical simulation to the modeling of IC process yields

Author

Sanders, Thomas J. ; Means, Dale P. ; Hess, Glenn T.

Author_Institution

Florida Inst. of Technol., Melbourne, FL, USA

fYear

1999

fDate

1999

Firstpage

191

Lastpage

195

Abstract

This paper presents the results of an R&D program conducted jointly by a small business and a university. The goal of the program is to develop a new methodology for IC process and device simulation. The core of the methodology is a software program called STADIUM, which enables process and device engineers to include in their designs the effects of manufacturing variation on product yield. STADIUM is used to develop statistical information about integrated circuit parameters using a statistical technique called design of experiments. The results of the simulation can then be related to potential failure modes and to product yield. This paper describes the algorithms and user interface contained in the software

Keywords

design of experiments; electronic engineering computing; failure analysis; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; research initiatives; software packages; IC process simulation; IC process yields; R&D program; STADIUM; algorithms; design of experiments; device simulation; integrated circuit parameters; methodology; modeling; potential failure mode; product yield; small business; software program; statistical information; statistical simulation; university; user interface; Application specific integrated circuits; Circuit simulation; Contracts; Design engineering; Equations; Integrated circuit modeling; Integrated circuit yield; Manufacturing processes; Physics; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 1999. Proceedings of the Thirteenth Biennial

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-5240-8

Type

conf

DOI

10.1109/UGIM.1999.782851

Filename

782851