Title :
Diagnostic test pattern generation for sequential circuits
Author :
Hartanto, Ismed ; Boppana, Vamsi ; Patel, Janak H. ; Fuchs, W. Kent
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
fDate :
27 Apr-1 May 1997
Abstract :
A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at primary input in the modified circuit techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits. Speed-up of the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic
Keywords :
VLSI; automatic testing; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; state estimation; ATPG process; circuit netlist modification; computational effort; diagnostic test pattern generation; forced value; primary input; sequential circuits; state identification; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Fault diagnosis; Logic devices; Performance evaluation; Sequential analysis; Sequential circuits; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600264
