A high-resolution time-to-digital converter based on multi-phase clock implement in field-programmable-gate-array

In this paper, a time-to-digital converter (TDC) based on 4 multi-phase clocks is implemented in a XILINX´s Virtex4 FPGA. Profit from the PLL technology we can adjust the clock phase precisely. In this case, 4 multi-phase clocks have the 0°, 90°, 180°, 270° phase shift are generated. Each clock´s rising edge has the same delay to the previous clock. Based on those 4 multi-phase clocks, we can divide one clock period into 4 same parts. The bin size of the TDC can be proved to 1/4 clock period. It is a new approach to come true the time interpolation within one clock period. The TDC based on multi-phase clock needs less logic resource than other kind TDC. Its high precision, high integrated level and large dynamic range can fit the demands very well. The performance of the multi-phase clock based TDC was tested. The bin size (resolution) of each channel is 0.757ns and the RMS (precision) is less than 0.5ns. The dynamic range is longer than 1 second. 64 TDC channels are realized in only one FPGA on a 15cm * 15cm board.