DocumentCode
3041738
Title
A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography
Author
Sagara, K. ; Kure, T. ; Shukuri, S. ; Yugami, J. ; Hasegawa, N. ; Shinriki, H. ; Goto, H. ; Yamashita, H. ; Takeda, E.
Author_Institution
Hitachi Ltd., Tokoyo, Japan
fYear
1992
fDate
2-4 June 1992
Firstpage
10
Lastpage
11
Abstract
A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<>
Keywords
DRAM chips; VLSI; photolithography; 0.25 micron; 256 Mbit; CVD-W plate technology; DRAMs; RSTC structure; cell capacitance; fine-pattern delineation; quarter-micron phase-shift lithography; recessed stacked capacitor; Capacitance; Degradation; Fabrication; Laboratories; Lithography; MOS capacitors; Random access memory; Silicon; Space technology; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Conference_Location
Seattle, WA, USA
Print_ISBN
0-7803-0698-8
Type
conf
DOI
10.1109/VLSIT.1992.200618
Filename
200618
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