Title :
A buried-plate trench cell for a 64-Mb DRAM
Author :
Kenney, D. ; Parries, P. ; Pan, P. ; Tonti, W. ; Cote, W. ; Dash, S. ; Lorenz, P. ; Arden, W. ; Mohler, R. ; Roehl, S. ; Bryant, A. ; Haensch, W. ; Hoffmann, B. ; Levy, M. ; Yu, A.J. ; Zeller, C.
Author_Institution :
IBM Gen. Technol. Div., Essex Junction, VT, USA
Abstract :
A technology for fabricating a 64-Mb DRAM is described. The basic cell concept is an evolution from IBM´s SPT cell and a modified SPT cell. Ground-rule shrinkage and additional features permit the realization of a cell size of 1.5 mu m/sup 2/. The chip incorporates N-array transfer gates isolated from the P-substrate by an intervening buried N-layer which forms the buried plate for the trench capacitor. The N-array devices, isolated P-well, and low-resistance wordline conductors provide a dense cell with superior soft-error-rate (SER) protection. Density improvement is achieved by the use of fully borderless contacts and ground-rule shrinkage. The interconnects use a Damascene metallization scheme that repeatedly applies chemical-mechanical polishes for dielectrics and metals.<>
Keywords :
DRAM chips; VLSI; integrated circuit technology; metallisation; polishing; 64 Mbit; DRAM; Damascene metallization scheme; N-array transfer gates; buried-plate trench cell; chemical-mechanical polishes; dense cell; fully borderless contacts; ground-rule shrinkage; isolated P-well; low-resistance wordline conductors; modified SPT cell; soft-error-rate; Boron; Capacitors; Chemicals; Conductors; Dielectrics; Isolation technology; Metallization; Protection; Random access memory; Tungsten;
Conference_Titel :
VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0698-8
DOI :
10.1109/VLSIT.1992.200620
