Title :
An ultra high speed ECL-bipolar CMOS technology with silicon fillet self-aligned contacts
Author :
Liu, T.M. ; Chin, G.M. ; Morris, M.D. ; Jeon, D.Y. ; Archer, V.D. ; Kim, H.H. ; Cerullo, M. ; Lee, K.F. ; Sung, J.M. ; Lau, K. ; Chiu, T.Y. ; Voshchenkov, A.M. ; Swartz, R.G.
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
Abstract :
An ultra-high-speed half-micron non-overlapped super self-aligned BiCMOS technology that uses a silicon fillet self-aligned contact technology (SIFT) for both bipolar and MOS transistors is discussed. The SIFT process reduces the device capacitances and series resistances by minimizing the diffusion region area as well as the polysilicon electrode area. Deep trench isolation for bipolar transistors allows the device area to be much reduced for VLSI applications. The ECL gate delay is demonstrated to be 31 ps for devices with emitter polysilicon widths of 0.6 mu m. The CMOS ring oscillator gate delays are 58 ps for 0.5- mu m gate length and 67 ps for 0.6- mu m gate length at 5 V.<>
Keywords :
BiCMOS integrated circuits; VLSI; digital integrated circuits; emitter-coupled logic; integrated circuit technology; oscillators; 0.5 to 0.6 micron; 31 to 67 ps; 5 V; BiCMOS technology; CMOS ring oscillator gate delays; ECL gate delay; ECL-bipolar CMOS technology; SIFT process; Si-fillet self-aligned contact technology; VLSI; bipolar transistors; device capacitances; diffusion region area; digital IC; emitter polysilicon; gate length; polysilicon electrode area; reduced device area; self-aligned contacts; series resistances; super self-aligned; trench isolation; ultra-high-speed; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Capacitance; Delay; Electrodes; Isolation technology; MOSFETs; Silicon; Very large scale integration;
Conference_Titel :
VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0698-8
DOI :
10.1109/VLSIT.1992.200631
