DocumentCode :
3041960
Title :
CMOS differential pass-transistor logic (CMOS DPTL) predischarge buffer design
Author :
Kayed, Somia I. ; Ragaei, Hani F.
Author_Institution :
Nucl. Mater. Authority, Cairo, Egypt
fYear :
1996
fDate :
19-21 Mar 1996
Firstpage :
527
Lastpage :
535
Abstract :
In both NMOS and CMOS PTL techniques, the problem of noise immunity limits applications which suffer from relatively low logic swings. Noise voltages, can degrade system performance and even produce faulty circuit operation. So, we propose an alternative pass-transistor configurations that directly address noise-immunity. Differential Pass Transistor Logic (DPTL) is a powerful configuration in CMOS technology. DPTL buffers has the ability to generate standard CMOS levels regardless of input signal-swing variation while providing noise immunity by maintaining the structural symmetry
Keywords :
CMOS logic circuits; buffer circuits; integrated circuit noise; logic design; CMOS DPTL; CMOS differential pass-transistor logic; noise immunity; predischarge buffer design; signal swing; structural symmetry; CMOS logic circuits; CMOS technology; Circuit faults; Circuit noise; Degradation; MOS devices; Noise generators; Signal generators; System performance; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radio Science Conference, 1996. NRSC '96., Thirteenth National
Conference_Location :
Cairo
Print_ISBN :
0-7803-3656-9
Type :
conf
DOI :
10.1109/NRSC.1996.551142
Filename :
551142
Link To Document :
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