A high performance 0.6 mu m BiCMOS SRAM technology with emitter-base self-aligned bipolar transistors and retrograde well for MOS transistors

Author

Honda, H. ; Uga, K. ; Ishida, M. ; Ishigaki, Y. ; Takahashi, J. ; Shiomi, T. ; Ohbayashi, S. ; Kohno, Y.

Author_Institution

Mitsubishi Electric Co., Hyogo, Japan

fYear

1992

fDate

2-4 June 1992

Firstpage

34

Lastpage

35

Abstract

The described technology uses a quintuple poly-Si and double-metal process architecture. The emitter and base of a bipolar transistor are self-aligned. The retrograde well for MOS transistors and the P isolation for bipolar transistors are formed by using high-energy ion implantation, while the concentration of the collector is determined by an N epitaxial layer only. As thick oxide remains at the base region before sidewall formation of MOS transistors, an ideal base current flows. The delay times of ECL, CMOS, and BiNMOS are 87 ps, 97 ps, and 130 ps, respectively. BiNMOS has a speed advantage over CMOS down to 2.5 V. A 5-ns 256 K (32 K*8) TTL SRAM has been fabricated with a 0.6- mu m BiCMOS SRAM technology.<>

Keywords

BiCMOS integrated circuits; SRAM chips; VLSI; integrated circuit technology; ion implantation; 0.6 micron; 2.5 V; 256 kbit; 32 kbyte; 5 ns; 87 to 130 ps; BiCMOS SRAM technology; BiNMOS; CMOS; ECL; MOS transistors; N epitaxial layer; P isolation; TTL compatible SRAM; delay times; double-metal process architecture; high-energy ion implantation; ideal base current; poly Si; retrograde well; self-aligned bipolar transistors; self-aligned emitter-base transistors; BiCMOS integrated circuits; Bipolar transistors; Boron; Capacitance; Electrodes; Epitaxial layers; Ion implantation; MOSFETs; Oxidation; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0698-8

Type

conf

DOI

10.1109/VLSIT.1992.200633

Filename

200633