Title :
Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics
Author :
Verbeek, Freek ; Schmaltz, Julien
Author_Institution :
Inst. for Comput. & Inf. Sci., Radboud Univ. Nijmegen, Nijmegen, Netherlands
Abstract :
In the multi-core era, ensuring deadlock freedom of communication fabrics is an important challenge. Intel proposed xMAS, a microarchitecture description language (MaDL), to support the formal modelling and verification of communication fabrics. The xMAS language is restricted to eight basic primitives. Using this restriction, an efficient deadlock detection technique has been defined. This technique is tailored to the eight primitives, which are not sufficient to model many realistic designs. We exhibit two primitives, namely, an adaptive switch and a synchronization barrier, that cannot be expressed or analyzed using the current xMAS language and tools. Our main contribution is to automatically generate an efficient deadlock detection algorithm tailored to a given set of primitives. We define a set of core primitives and extension mechanisms for user-defined primitives. This creates a family of MaDL´s together with a family of tailored and efficient deadlock detection algorithms. We prove that the automatically generated algorithms are correct by construction, i.e., they correctly detect deadlocks in all fabrics defined in the language for which they are generated. These algorithms handle message dependencies, counters, virtual channels, parametric buffer sizes, and many other aspects of micro-architectural models. The effectiveness of our approach is demonstrated on models with adaptive switches and synchronization barriers. Our approach automatically provides efficient deadlock detection for a large family of MaDL´s.
Keywords :
concurrency control; formal verification; hardware description languages; multiprocessing systems; network-on-chip; synchronisation; MaDL; adaptive switch; automatic deadlock detection algorithm generation; communication fabrics; core primitives; counters; formal modelling; formal verification; message dependencies; microarchitecture description languages; multicore era; parametric buffer sizes; synchronization barrier; user-defined primitives; virtual channels; xMAS language; Detection algorithms; Equations; Fabrics; Mathematical model; Semantics; Syntactics; System recovery;
Conference_Titel :
High Level Design Validation and Test Workshop (HLDVT), 2012 IEEE International
Conference_Location :
Huntington Beach, CA
Print_ISBN :
978-1-4673-2897-5
DOI :
10.1109/HLDVT.2012.6418239