Title :
BiFAMOS technology for high speed mega-bit EPROMs
Author :
Hu, G.J. ; Tran, L.C. ; Keshtbod, P. ; Segal, J. ; Park, K.H. ; Amin, T. ; Prickett, B. ; Tsao, S.C. ; Yen, J. ; Smith, E. ; Bornstein, J. ; Alvarez, A.R.
Author_Institution :
Cypress Semiconductor, San Jose, CA, USA
Abstract :
An advanced BiCMOS floating gate avalanche MOS (BiFAMOS) technology for high-speed and high-density EPROM applications is described. It is of great interest to develop chips with access times of 20 ns or less to support 33-to-50-MHz systems without a SRAM interface. Since channel hot carrier injection is used in EPROM programming, the high-current and high-voltage programming conditions limit the size of the FET that can be used in the cell and hence the low cell current directly affects speed. A two-transistor cell has been previously introduced to overcome this speed limitation but at the expense of area. Here, BiCMOS technology is used to alleviate this speed/area tradeoff. Fast bipolar sense amplifiers and high-current NPN drivers allow very-high-speed access without a large cell current. With a 1-T cell, an access time of 12 ns was obtained on a 1-Mb EPROM, demonstrating that this 0.8- mu m BiFAMOS is capable of sub-20-ns 4M EPROMs.<>
Keywords :
BiCMOS integrated circuits; EPROM; PLD programming; VLSI; integrated circuit technology; 0.8 micron; 1 Mbit; 1-T cell; 12 ns; 33 to 50 MHz; 4 Mbit; BiCMOS floating gate avalanche MOS; BiCMOS technology; BiFAMOS technology; EPROM programming; VLSI; access times; bipolar sense amplifiers; channel hot carrier injection; high-current NPN drivers; high-density EPROM; mega-bit EPROMs; speed/area tradeoff; CMOS technology; Circuits; EPROM; FETs; Hot carrier injection; Implants; MOS devices; Random access memory; Thermal resistance; Voltage;
Conference_Titel :
VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0698-8
DOI :
10.1109/VLSIT.1992.200637
