A novel cell structure for giga-bit EPROMs and flash memories using polysilicon thin film transistors

Author

Koyama, S.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1992

fDate

2-4 June 1992

Firstpage

44

Lastpage

45

Abstract

A cell structure using poly Si TFTs (thin film transistors) to realize half-micron channel length, channel width, and isolation space is described. This structure also reduces the drain capacitance relative to conventional structures with cells fabricated on Si substrate with channel doping. A fully-self-aligned polySi TFT cell process sequence without complex SOI technologies such as SIMOX or laser recrystallization is developed. A study of the read-out operation indicates that the application of the TFT cells for EPROMs and flash memories is advantageous not only for access time improvement but also for cell scalability.<>

Keywords

EPROM; MOS integrated circuits; VLSI; integrated circuit technology; thin film transistors; 0.5 micron; Si substrate; TFT cell; TFT cells; TFTs; VLSI; access time improvement; cell scalability; cell structure; drain capacitance; flash memories; giga-bit EPROMs; giga-bit memories; polycrystalline Si; polysilicon thin film transistors; read-out operation; self-aligned polysilicon TFT process; Capacitance; EPROM; Flash memory; Immune system; Insulation; Isolation technology; Leakage current; Space technology; Substrates; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0698-8

Type

conf

DOI

10.1109/VLSIT.1992.200638

Filename

200638