DocumentCode :
3042088
Title :
Single-source hardware modeling of different abstraction levels with State Charts
Author :
Findenig, R. ; Leitner, Thomas ; Ecker, Wolfgang
Author_Institution :
Upper Austrian Univ. of Appl. Sci., Hagenberg, Austria
fYear :
2012
fDate :
9-10 Nov. 2012
Firstpage :
41
Lastpage :
48
Abstract :
This paper presents an approach and a framework for hardware modeling on different abstraction levels, from untimed to cycle-accurate. Being based on UML State Charts, the graphical input language is intuitive to use and can directly serve as the documentation of the model. Compared to previous approaches, we propose an extension to UML that allows specifying all supported abstraction levels of a model in a single source, easing both development and debugging. We also present a code generator that allows selecting a specific abstraction level from the model to automatically generate SystemC code for it. Additionally, we use a modeling style extending existing work for purely cycle-accurate State Charts so that a previously presented code generation approach for VHDL can be reused.
Keywords :
Unified Modeling Language; hardware description languages; program compilers; system documentation; visual languages; UML extension; UML state charts; abstraction levels; automatic SystemC code generation approach; graphical input language; model documentation; single-source hardware modeling; Abstracts; Clocks; Computational modeling; Concrete; Generators; Hardware; Unified modeling language;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Level Design Validation and Test Workshop (HLDVT), 2012 IEEE International
Conference_Location :
Huntington Beach, CA
ISSN :
1552-6674
Print_ISBN :
978-1-4673-2897-5
Type :
conf
DOI :
10.1109/HLDVT.2012.6418241
Filename :
6418241
Link To Document :
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