DocumentCode :
3042158
Title :
The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems
Author :
Braga, Diego ; Fummi, F. ; Pravadelli, Graziano ; Vinco, S.
Author_Institution :
Dept. of Comput. Sci., Univ. of Verona, Verona, Italy
fYear :
2012
fDate :
9-10 Nov. 2012
Firstpage :
76
Lastpage :
83
Abstract :
Modern embedded systems require a tight integration among several heterogeneous components including digital and analog HW, as well as HW-dependent SW. In literature there is a lack of a complete approach, allowing reuse and at the same time supporting correct integration of heterogeneous components. Indeed, traditional approaches rely either on homogeneous top-down methodologies (that do not allow reuse) or on co-simulation (that does not guarantee correct integration). This paper proposes to combine IP-XACT and UNIVERCM. The former is an IEEE standard for specifying interface and communication style of digital IPs. The latter is a computational model that allows to represent the starting heterogeneous components in a homogeneous way. In this way, IP-XACT is used in this paper to support the integration of general heterogeneous components, to extract component interfaces and to generate the necessary connecting modules. Furthermore, UNIVERCM allows to generate a homogeneous representation of the components behavior (in a bottom-up flow) to allow simulation and validation of the generated components and of the final system. Thus, this strange pair allows integration and validation of system communication. The effectiveness of this novel approach has been proven on complex heterogeneous benchmarks.
Keywords :
IEEE standards; embedded systems; formal specification; logic circuits; logic design; HW-dependent SW; IEEE standard; IP-XACT; UNIVERCM; analog HW; communication style specification; component behavior; component interface extraction; digital HW; digital IP; heterogeneous components; heterogeneous embedded system integration; interface specification; system communication; IP networks; Joining processes; Ports (Computers); Protocols; Standards; Transducers; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Level Design Validation and Test Workshop (HLDVT), 2012 IEEE International
Conference_Location :
Huntington Beach, CA
ISSN :
1552-6674
Print_ISBN :
978-1-4673-2897-5
Type :
conf
DOI :
10.1109/HLDVT.2012.6418246
Filename :
6418246
Link To Document :
بازگشت