Title :
Perimeter effects in small geometry bipolar transistors
Author :
Lee, W. ; Sun, J.Y.-C. ; Warnock, J. ; Jenkins, K.A.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
The fundamental limits on device performance imposed by geometrical effects are studied. Results of an extensive three-dimensional (3D) device simulation study are given and compared with experimental results of a 0.25- mu m bipolar technology. It is shown in this study that geometrical factors alone can result in lower DC current gain and lower f/sub T/ at low current densities for smaller devices. It is also shown that perimeter effects are beneficial for small emitter devices at high current densities. This is a particularly important design consideration for high current operation as in BiCMOS gates.<>
Keywords :
bipolar transistors; semiconductor device models; size effect; 0.25 micron; 3D drift diffusion simulation; BiCMOS gates; DC current gain; Gummel plot; common emitter current gain; cutoff frequency; geometrical effects; high current densities; high current operation; perimeter effects; small emitter devices; small geometry bipolar transistors; Bipolar transistors; Current density; Current measurement; Cutoff frequency; Density measurement; Frequency measurement; Gain measurement; Geometry; Neural networks; Paper technology;
Conference_Titel :
VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0698-8
DOI :
10.1109/VLSIT.1992.200644
