Post-silicon verification and debugging with control flow traces and patchable hardware

In this paper we show three methods for postsilicon verification and debugging with control-flow analysis. By concentrating on control flows of SoC behavior, abstracted analysis can be applied and much significantly long time spans can be examined. The first method introduces monitoring methods of communications or transactions among cores inside SoCs. From the monitoring results, control sequences on interactions of cores are automatically determined to be used for post-silicon analysis. The second method shows algorithms to determine orderings of communications inside NoC (Network-on-Chip) used in SoCs. These analysis give information on how messages are transferred onto NoC, which are to be used for post-silicon analysis. The third method introduces trace buffers to compactly save state transition sequences of FSMs in the control parts of cores inside SoCs. By recognizing abnormal transitions, which is basically control flow analysis, both logical and electrical errors can be efficiently detected during postsilicon debug.