DocumentCode
3042244
Title
A CPLD-based design of pre-processing circuit in navigation computer
Author
Xuan Xiao ; Mengyin Fu ; Qingzhe, Wang ; Xin, Yang
Author_Institution
Sch. of Autom., Beijing Inst. of Technol., Beijing, China
fYear
2010
fDate
8-10 June 2010
Firstpage
1204
Lastpage
1207
Abstract
In order to improve the processing speed of navigation computer, a CPLD-based design of preprocessing circuit is presented. The outputs of gyroscopes, accelerometers, odometer and GPS are pre-processed, and then exchanged with the signal processing circuit through a dual-port RAM. All the information pre-processing circuit is designed in the CPLD, which enables a more flexible using and simpler circuit composition.
Keywords
digital signal processing chips; programmable logic devices; random-access storage; CPLD-based design; GPS; accelerometer; circuit composition; complex programmable logic device; digital signal processor; dual-port RAM; gyroscope; navigation computer; odometer; preprocessing circuit; processing speed; signal processing circuit; Accelerometers; Demodulation; Digital signal processing; Finite impulse response filter; Gyroscopes; Navigation; Temperature distribution;
fLanguage
English
Publisher
ieee
Conference_Titel
Systems and Control in Aeronautics and Astronautics (ISSCAA), 2010 3rd International Symposium on
Conference_Location
Harbin
Print_ISBN
978-1-4244-6043-4
Electronic_ISBN
978-1-4244-7505-6
Type
conf
DOI
10.1109/ISSCAA.2010.5633097
Filename
5633097
Link To Document