A high performance Si on Si multichip module technology

A high-performance microprocessor and cache core based on a silicon-on-silicon multichip module technology is discussed. The technology was designed to have low interconnect parasitics and low cost. A 12-chip module operating at over 75 MHz using this technology was built incorporating an i486 microprocessor, a cache controller, and 256 K of SRAM cache. This represents a 40-50% clock rate improvement over a conventional packaged part approach. The dice were attached to a four-layer metal and polyimide silicon substrate using controlled collapse chip connection (C4) technology. The unit was assembled into a 350 pin ceramic pin grid array (PGA) package. A low-dielectric-constant polyimide and a flip chip die interconnection process minimized RC delay and inductance, and the module can operate at over 160 MHz. The module can dissipate up to 20 W using an array of thermal bumps spaced over the die surface and attached to staircase vias through the substrate.<>