A high performance asymmetric LDD MOSFET using selective oxide deposition technique

Author

Horiuchi, T. ; Homma, T. ; Murao, Y. ; Okumura, K.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1992

fDate

2-4 June 1992

Firstpage

88

Lastpage

89

Abstract

It is shown that a 45% on-current increase can be achieved for an MOSFET without sacrificing hot carrier immunity by applying an asymmetric LDD sidewall spacer technology. The asymmetric spacer is fabricated by using a selective oxide deposition technique, which gives a wide design feasibility of implementing asymmetric structures in the CMOS process. The process requires no additional masking steps and is independent of wafer orientation. Based on an optimized asymmetric LDD design, 5-V operation of a 0.45- mu m nMOSFET is demonstrated. A simple on-current model for asymmetric LDD is also presented.<>

Keywords

CMOS integrated circuits; hot carriers; insulated gate field effect transistors; integrated circuit technology; oxidation; 0.45 micron; CMOS process; LDD MOSFET; asymmetric LDD sidewall spacer technology; hot carrier immunity; nMOSFET; on-current model; selective oxide deposition; CMOS technology; Chemical processes; EPROM; Fabrication; Implants; Ion implantation; MOSFET circuits; National electric code; Paper technology; Passivation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0698-8

Type

conf

DOI

10.1109/VLSIT.1992.200662

Filename

200662